1. Field of the Invention
The invention relates to a method for reducing power consumption, and more particularly to a method for reducing power consumption for a device employing a system on chip (SOC) while the SOC is in the fully operational mode.
2. Description of the Related Art
A modern system on chip (SOC) is provided for high speed processes and comprises one or more processor cores and a memory directly attached and coupled to the one or more processor cores. Currently, the modern SOC is fabricated with advanced semiconductor process technologies, achieving greatly reduced widths and lengths of transistor gates. However, the problem of static leakage current increases with deeper sub-micro region fabrication of modern SOCs.
Thus, saving power is an important feature for devices employing modern SOCs. For conventional power saving methods, a device employing a modern SOC can operate in an operation mode or a power saving mode. When the device is in the operation mode, a power source must continue to supply power to a memory directly attached and one or more processor cores of the device. As a result, static current leakage of the directly attached memory is a major drain on the power source of a device in the operation mode. When the device is in the power saving mode, the modern SOC is no longer operating at a highest clock rate, wherein operating frequency of the modern SOC is lowered or halted.
Thus, it is desired to provide a method and a system for reducing power consumption, in which power can be saved while the system remains in the operation mode.